Intel and SambaNova simply constructed a three-chip AI machine that splits work between GPUs, RDUs, and Xeon

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GPUs deal with prefill operations by changing prompts into key-value cachesSambaNova RDUs generate tokens at excessive throughput and low latencyIntel Xeon 6 processors handle workload distribution and execute compiled code Intel and SambaNova Techniques have launched a joint {hardware} blueprint combining GPUs, SambaNova RDUs, and Intel Xeon 6 processors for large-scale inference workloads.

The system assigns GPUs to prefill operations, RDUs to decoding, and Xeon CPUs to execution and orchestration duties throughout agent-driven environments.

“Agentic AI is shifting into manufacturing — and the successful sample we’re seeing is GPUs to begin the job, Intel Xeon 6 to run it, and SambaNova RDUs to complete it quick,” stated Rodrigo Liang, CEO and co-founder of SambaNova Techniques.

Article continues beneath Chances are you'll like CPU is the execution and management layer This design is scheduled to be obtainable within the second half of 2026 for enterprises, cloud suppliers, and sovereign deployments.

The structure locations Intel Xeon 6 processors on the middle of system management, the place they handle workload distribution, execute code, and coordinate instrument interactions.

It contains dealing with compilation, validating outputs, and sustaining communication between simultaneous processes.

“When 1000's of simultaneous coding brokers are producing instrument calls, retrieval requests, code builds, and encrypted inter-agent messages, the CPU will not be a background part — it's the system’s government and motion layer,” stated Harry Ault, CRO of SambaNova.

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The assertion defines the CPU as the first layer liable for system habits somewhat than a supporting part.

In response to SambaNova, Xeon 6 delivers greater than 50% quicker LLVM compilation occasions in contrast with Arm-based server CPUs.

It additionally delivers as much as 70% quicker vector database efficiency in contrast with different x86-based techniques.

What to learn subsequent These figures relate to execution velocity inside coding and retrieval workflows, and on this configuration, GPUs course of the prefill stage by changing prompts into key-value caches.

SambaNova RDUs function because the decoding layer, producing tokens at excessive throughput and low latency.

Xeon 6 processors operate as each host CPUs and execution engines, managing system-level operations and working compiled workloads.

“Manufacturing inference is shifting towards heterogeneous {hardware} — no single chip kind is perfect for each stage of an agentic workflow,” stated Banghua Zhu, co-founder and CTO at RadixArk.

He added that combining RDUs with Xeon CPUs permits techniques to keep up compatibility with present software program environments.

The system is designed to run inside present air-cooled knowledge facilities with out requiring new builds.

In response to the businesses, this permits scaling of inference workloads with out extra pressure on water and power sources.

As Nvidia and Groq proceed to deal with bettering inference throughput and latency, this announcement provides a layer of competitors.

It provides an alternate method that distributes workloads throughout a number of {hardware} layers somewhat than counting on a single processing mannequin.

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