Subsequent gen AMD EPYC processor, codenamed Venice is the primary HPC product to make use of TSMC’s N2 node – however I’m wondering if Apple was there first

AMD reveals off its first 2nm-class Venice CPU die constructed utilizing TSMC’s N2 nodeVenice, constructed on Zen 6, targets high-performance computing workloadsAMD and TSMC hope to deepen their collaboration for future improvements

AMD has introduced it has efficiently produced the primary 2nm-class silicon for its next-generation EPYC processor, codenamed “Venice” which is predicted to launch in 2026 as a part of AMD’s sixth Era EPYC lineup.